Method of testing a circuit using an output vector

ABSTRACT

A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

TECHNICAL FIELD

[0001] This invention relates generally to integrated circuit devicesand, more specifically, to a circuit and method for controlling theability of such devices to enter into a test mode.

BACKGROUND OF THE INVENTION

[0002] The testing of memory devices in the prior art generally involvesreceiving inputs from several memory addresses at one time into a testvector decoding circuit and performing logic functions on those inputs.The resulting output test vectors are used to perform operations onvarious devices, such as compressing address circuits or disablingregulators. Once testing has been completed, the values of the outputtest vectors will remain consistent for the purpose of driving circuitsduring non-test operations of the memory device.

[0003] One possible method of triggering the test mode as disclosed inthe prior art is to use two signals. For example, a WCBR signal (Writeenable signal at low with the CAS signal transmitted Before the RASsignal) sent during the transmission of a supervoltage signal is oftenused. The supervoltage signal will have a higher potential than thestandard supply voltage. This supervoltage signal may generally beapplied consistently throughout both test and non-test modes of thememory device. Only during the test mode, however, will the WCBR signaldeliberately appear.

[0004] Nevertheless, it is possible that placing the memory device in anoisy environment may result in an errant WCBR signal being sent to thetest vector decode circuit during a non-test mode. For example, memorydevices are often subjected to a burn-in process, wherein the memorydevices are operated at higher-than-usual voltages and temperatures inorder to identify weak memory devices. This noisy process could resultin random signals being transmitted through the write enable, CAS, andRAS paths so as to trigger a false WCBR signal and latch the test vectordecode circuit. In that event, the test vector decode circuit wouldprocess the memory address inputs at their present random state. Theresulting output vectors might not have the proper values. As aconsequence, parts of the integrated device that should receive aparticular value may no longer do so. For example, it is possible thatone of the output vectors may represent an errant “ground V_(BB)” signaltransmitted at the wrong time. That would ground the substrate of thememory device, thereby causing a high current mode and eventual meltdownof the circuitry. Therefore, it would be a benefit to the art to be ableto prevent the memory circuit from inadvertently entering a test mode.

SUMMARY OF THE INVENTION

[0005] Accordingly, one embodiment of the present invention provides alockout circuit for an operations circuit. The operations circuit isconfigured to receive one or more sets of inputs. Upon receiving alatching signal, the operations circuit performs a decode operation onthe present set of inputs A₀ through A_(n). The decode operation, inturn, establishes a value for one or more output vectors in response toa latch signal. Further, a disable vector is included as one of theoutput vectors. At least one of the input sets is configured toestablish a lockout value for the disable vector. Thus, once theappropriate set is input and latched, the resulting disable vectorprevents inadvertent latching signals from reaching the operationscircuit. However, the operations circuit is also configured to receive areset signal and reset the disable vector in response to that signal.

[0006] In another embodiment, the operations circuit is a test vectordecode circuit configured to receive a supervoltage signal. Thesupervoltage signal is generally maintained during all operations of thetest vector decode circuit. The test vector decode circuit is configuredto reset all output vectors in response to turning off the supervoltagesignal. In addition, the latching signal is combined with the disablevector through logic circuitry before reaching the test vector decodecircuit. Latching operations proceed as described above until thedisable vector changes the logic circuitry output, thereby locking outfurther latching signals. Once that occurs, the output vectors will notchange unless the supervoltage signal is removed. In that event, all ofthe test vectors would be reset and any errors in the operation of thememory circuit could more likely be traced to the interruption of thesupervoltage signal rather than to inadvertent latching signals. Thus,in addition to the advantages of preventing inadvertent activation ofthe test mode using a minimal amount of die space, this embodiment alsosimplifies error detection and correction.

[0007] Still other exemplary embodiments operate similarly but usedifferent logic circuitry configurations. Further, the test vectordecode circuits in these embodiments are configured to enable latchingand resetting in a manner consistent with the logic circuitryconfigurations.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 depicts a schematic diagram of a test mode circuit asexists in the prior art.

[0009]FIG. 2 is a timing diagram illustrating the combined input signalsused, both in the prior art and in an exemplary embodiment of theclaimed invention, to latch the test vectors to output.

[0010]FIG. 3 is a schematic diagram of one exemplary embodiment of thepresent invention.

[0011]FIG. 4 is a schematic diagram of a second exemplary embodiment ofthe present invention.

[0012]FIG. 5 is a schematic diagram of a third exemplary embodiment ofthe present invention.

[0013]FIG. 6 is a schematic diagram of a fourth exemplary embodiment ofthe present invention.

[0014]FIG. 7 is a schematic diagram of a fifth exemplary embodiment ofthe present invention.

[0015]FIG. 8 is a schematic diagram of a sixth exemplary embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] As FIG. 1 demonstrates, testing the operation of a memory circuitas taught by the prior art is generally performed by directing signalsto a test vector decode circuit 10 from a plurality of memory addressesA₀ through An, wherein n is an integer. The test vector decode circuit10 is usually a multiplexer, but regardless of the specificconfiguration of the test vector decode circuit 10, it will subject theinputs to one or more logic operations and generate a plurality ofoutput test vectors V₀ through Vm, wherein m is an integer that may ormay not be equal to integer n. In addition, a supervoltage detectcircuit 12 is provided and is configured to respond to an externalsignal P by transmitting a supervoltage signal (SV) to a reset inputterminal 14 of the test vector decode circuit 10. The test vector decodecircuit 10 resets all output test vectors V₀ through Vm in response to alow SV signal. Thus, as long as SV remains at a high supervoltagepotential, the output test vectors V₀ through Vm maintain the valuesestablished as of the last logic operation. Logic operations areinitiated by a signal sent to a latch input terminal 16 of the testvector decode circuit 10. In this embodiment, the test vector decodecircuit 10 is configured to allow latching of the output test vectors V₀through Vm in response to a low WCBR signal, designated in FIG. 1 asWCBR*. This WCBR* signal is output by a WCBR detect circuit 18 whichreceives the signals RAS (Row Address Strobe), CAS (Column AddressStrobe), and WE (Write Enable). FIG. 2 demonstrates the required stateof these signals in order to latch the output test vectors: if (1) WE islow, and (2) CAS transmits a low signal before RAS does, then the WCBRcircuit will output a WCBR* signal for latching the output test vectorsV₀ through Vm. FIG. 2 also illustrates the cycle length of the testvectors in relation to the duration of the three signals. After theoutput test vectors V₀ through Vm have been latched, they are used todrive external devices. Further inputs and latchings may be used toalter the drive of these external devices. Once testing is over,however, the drive signals should generally maintain their value.

[0017] The combination of signals generating WCBR is chosen to triggerthe latching of the output vectors because that combination is notintentionally used during non-test operations of the memory device. Thisreduces the chance of accidental latching and changing of the outputtest vectors at inappropriate times. As mentioned above, however, thatcombination of signals may appear as a glitch in noisy environments suchas the burn-in process.

[0018] In order to prevent such accidental latching and the resultingconsequences, a preferred embodiment of the present invention providesan additional output test vector V_(dis) that is used in conjunctionwith a logic unit such as an OR gate 20 to lock out further WCBR*signals. As shown in FIG. 3, the OR gate 20 is electrically interposedbetween the WCBR detect circuit 18 and the latch input terminal 16. As aresult, the WCBR* signal serves as a first input for the OR gate 20. Theoutput test vector V_(dis) serves as a second input for the OR gate 20.Initially, V_(dis) transmits a low signal and WCBR* transmits a highsignal. As a result, the OR gate 20 outputs a high signal and there isno latching.

[0019] When CAS is transmitted before RAS with WE at low, the WCBR*signal changes to low. The OR gate 20 recognizes the change.Accordingly, the output of OR gate 20 also changes to low and allowselectrical communication within the test vector decode circuit 10. As aresult of the decode operations performed on the inputs, the values ofone or more output vectors are established. If V_(dis) is one of theoutput vectors affected by the inputs, then V_(dis) will generate andmaintain a high signal. This signal, which can be described as a“lockout” signal for purposes of this application, changes the OR gate20 output back to a high signal. Regardless of further changes in theWCBR* signal, the OR gate 20 will continue to output a high signal aslong as V_(dis) is high. Thus, the high signal from V_(dis) blocks anyother output test vector from being latched, and the test mode is ended.The only way this test vector lockout mode can be changed is if a low SVsignal is transmitted to the reset input terminal 14. Doing so activatesthe reset function of the test vector decode circuit 10. Therefore, ifthe tested devices are operating in an unexpected manner, it is morelikely that such a problem would be due to the supervoltage signal andits related circuitry rather than to accidental latching of the outputtest vectors.

[0020] Moreover, the current invention covers other embodiments havingdifferent lockout configurations. For example, FIG. 4 illustrates thatthe OR gate can be replaced by another logic unit, such as a NOR gate22. While the required input values remain the same as in the previousembodiment, the test vector decode circuit 10 is now configured to allowlatching in response to a high signal received at the latch inputterminal 16. Thus, before lockout, V_(dis) transmits a low signal.Accordingly, the NOR gate 22 will transmit a high latch enable signal inresponse to-the low WCBR* input. Once the appropriate inputs are decodedto change the value of V_(dis) to a high signal, the NOR gate 22 willcontinue to transmit a low signal, regardless of further low WCBR*signals, until the output vectors are reset.

[0021] In addition to using other logic units, one could choose toenable a lockout mode in response to different inputs. In FIG. 5, thetest vector decode circuit 10 is once again configured to enablelatching in response to a high signal. In this embodiment, however, theenabling signal comes from the output of an AND gate 24. Furthermore,V_(dis) initially transmitting a high signal rather than a low one.Thus, latching will occur during this V_(dis) state when WCBR* is highrather than low. In order to lock out further WCBR* signals, the V_(dis)vector must be changed to low by decoding the proper input values.

[0022]FIG. 6 depicts yet another embodiment, wherein the test vectordecode circuit 10 is configured to allow latching in response to a lowsignal output from a NAND gate 26. As in the previous embodiment, a highWCBR* signal will cause latching only as long as V_(dis) transmits ahigh signal.

[0023] It should be further noted that WCBR* and SV are not the onlysignals that could be used to latch and reset the output vectors. Theyhave been identified in this specification for demonstrative purposesonly. FIG. 7 illustrates that, in general, all that is needed is somesort of operations circuit 28 configured to receive at least one inputA, perform some function based on that input, and transmit at least oneoutput B. In addition, the operations circuit 28 is configured toperform its function in response to receiving a function prompt signal30. However, that signal 30 is subject to being blocked by anyembodiment of the current invention, such as some form of lockoutcircuit 32. Nevertheless, the operations circuit 28 could be configuredto once again receive the latching prompt signal in response to a resetprompt signal 34.

[0024] One of ordinary skill can appreciate that, although specificembodiments of this invention has been described for purposes ofillustration, various modifications can be made without departing fromthe spirit and scope of the invention. For example, the memory devicecould be configured to provide a test vector lockout signal from anexternal device 22 that is independent from the test vector decodecircuit 10 and the output test vectors V₀ through Vm, as shown in FIG.8. Furthermore, resetting the test vector lockout signal could also beindependent from resetting all other output vectors. Such an embodimentcould comprise sending a reset signal directly to the external device22. Accordingly, the invention is not limited except as stated in theclaims.

What is claimed is:
 1. A test circuit for a device, comprising: a testvector decode circuit configured to receive at least one input signal,including a drive maintenance signal, and a latch enable signal, saidtest vector decode circuit further configured to transmit at least oneoutput signal to said device responsive to said latch enable signal,including a lockout signal further responsive to a reception of saiddrive maintenance signal; and a test vector recognition circuit coupledto said test vector decode circuit and configured to transmit said latchenable signal in response to a reception of a latch prompt signal, andsaid test vector recognition circuit further configured to receive saidlockout signal and overridingly exclude said latch enable signalresponsive to said lockout signal.
 2. The test circuit in claim 1,wherein said test circuit further comprises a reset circuit coupled tosaid test vector decode circuit and configured to reset said lockoutsignal in response to a reception of a reset prompt signal.
 3. A testmode regulation device for a decode circuit coupled to a plurality ofaddress input pathways, a reset signal pathway, and a plurality of testvector output pathways, and further configured to receive a latch enablepathway and perform at least one decode circuit operation, comprising:an additional test vector output pathway configured to couple to saiddecode circuit and further configured to transmit a disable signal inresponse to a final decode circuit operation; and a logic unitconfigured to electrically interpose between said latch enable pathwayand said decode circuit, wherein said logic unit comprises: a firstinput coupled to said latch enable pathway, a second input coupled tosaid additional test vector output pathway, and an output coupled tosaid decode circuit, and said logic unit configured to prevent a drivecommunication between said latch enable pathway and said decode circuitin response to said disable signal.
 4. The test mode regulation devicein claim 3, wherein said final decode circuit operation comprises alogic function performed on at least one signal from said plurality ofaddress input pathways.
 5. The test mode regulation device in claim 4,said additional test vector output pathway further configured totransmit an enable signal in response to a reset transmission from saidreset signal pathway; and said logic unit configured to reestablish saiddrive communication between said latch enable pathway and said decodecircuit in response to said enable signal.
 6. The test mode regulationdevice in claim 5, wherein said logic unit is an OR gate.
 7. A testdevice, comprising: a test vector decode circuit; an output node coupledto said decode circuit; and a lockout device coupled to said decodecircuit and configured to decouple said decode circuit from said outputnode after an operation of said decode circuit.
 8. The test device inclaim 7, said lockout device configured to decouple said output node inresponse to said operation of said decode circuit.
 9. A test vectordecode circuit comprising: a logic circuit; at least one input terminalcoupled to said logic circuit; a latch terminal coupled to said logiccircuit; at least one output terminal coupled to said logic circuit; anda latch disabling device coupled to said output terminal and to saidlatch terminal, said latch disabling device configured to activate inresponse to an output vector from said output terminal, and said outputterminal configured to transmit said output vector in response to acombination of: an input signal received at said input terminal, and alogic circuit operation.
 10. The test vector decode circuit in claim 9,further comprising a reset terminal coupled to said internal logiccircuit and configured to transmit a deactivation signal to said latchdisabling device through said internal logic circuit in response to areset signal received at said reset terminal.
 11. A test circuitcomprising: a test vector decode device; an input node coupled to saidtest vector decode device; an output node coupled to said test vectordecode device; a latch node; and a latch device coupled to said latchnode and configured to receive a latch prompt signal and furtherconfigured to alternatively receive an initial signal and an anti-latchsignal, said latch device further configured to allow electricalcommunication between said input node and said output node in responseto a combination of said initial signal and said latch prompt signal andto prevent said electrical communication in response to said anti-latchsignal.
 12. The circuit in claim 11, said input node configured toreceive a test-mode-end signal, said output node is coupled to saidlatch device, and said output node configured to transmit said initialsignal and to alternatively transmit said anti-latch signal in responseto: a reception of said test-mode-end signal by said input node; and areception of said latch prompt signal by said latch device.
 13. Thecircuit in claim 12, said output node further configured to couple to anexternal device.
 14. The circuit in claim 13, said output nodeconfigured to receive a signal maintaining voltage source.
 15. A testdecode system comprising: a decode circuit, farther comprising an outputnode configured to send at least one test drive transmission, includinga last test drive transmission; and a latch device coupled to saiddecode circuit and configured to allow electrical communication withinsaid decode circuit, and further configured to deactivate generallyconcurrently with said last test drive transmission from said outputnode.
 16. The test decode system in claim 15, said latch device coupledto said output node and further configured to deactivate responsive tosaid last test drive transmission.
 17. A lockout device for a decodecircuit having at least one decode function, including atest-mode-completion decode function comprising: a latch controlterminal configured to couple to said decode circuit and furtherconfigured to alternatively transmit: a lockout signal in response tosaid test-mode-completion decode function of said decode circuit, and anadmission signal; and a logic circuit, further comprising: an outputterminal configured to couple to said decode circuit, a first inputterminal configured to receive a decode initiation signal, said logiccircuit configured to initiate said decode function responsive to saiddecode initiation signal, and a second input terminal coupled to saidlatch control terminal and further configured to prevent said decodefunction responsive to said lockout signal.
 18. The device in claim 17,further comprising a mode shifter configured to couple to said decodecircuit, said mode shifter configured to transmit a reset signal inresponse to an external signal; and said latch control terminalconfigured to send said admission signal generally responsive to saidreset signal.
 19. The device in claim 18, said latch control terminalconfigured to retransmit said admission signal exclusively in responseto said reset signal.
 20. The device in claim 19, said mode shifterconfigured to couple to said latch control terminal through said decodecircuit.
 21. The device in claim 20, said mode shifter furtherconfigured to transmit a non-reset signal absent said external signal;and said decode circuit configured to receive a voltage source having afirst magnitude, and said non-reset signal has a voltage with a secondmagnitude greater than said first magnitude.
 22. The device in claim 21,said non-reset signal is a supervoltage signal.
 23. A signal maintainerfor an operations circuit configured to receive at least one input,perform a function on said input in response to a reception of afunction prompt signal, and transmit at least one output, comprising: alockout circuit configured to couple to said operations circuit, tocarry said function prompt signal to said operations circuit, and toreceive a lockout signal, and said lockout circuit further configured toselectively block any function prompt signal in response to a receptionof said lockout signal and to alternatively carry any function promptsignal to said operations circuit; an electrical communication componentcoupled to said lockout circuit and configured to carry said lockoutsignal.
 24. The signal maintainer in claim 23, said electricalcommunication component configured to further couple to said operationscircuit and to carry an output of said operations device to said lockoutcircuit.
 25. The signal maintainer in claim 24, said lockout circuitfurther configured to receive a reset prompt signal and refrain fromblocking said function prompt signal in response to a reception of saidreset prompt signal.
 26. The signal maintainer in claim 25, saidelectrical communication component further configured to carry saidreset prompt signal to said lockout circuit.
 27. A latch regulator for acircuit, comprising: a lockout pathway configured to carry a disablesignal having a first value and a second value; and a logic apparatushaving: a first input node coupled to said lockout pathway, a secondinput node configured to receive a latch prompt signal, and an outputnode configured to couple to said circuit, and said logic apparatusconfigured to recognize a change in said latch prompt signal while saiddisable signal has said first value and further configured to disregardsaid change in said latch prompt signal while said disable signal hassaid second value.
 28. The latch regulator in claim 27, said logicapparatus further configured to transmit a latch enable signal to saidcircuit in recognition of said change in said latch prompt signal. 29.The latch regulator in claim 28, said lockout pathway configured tocouple to an output terminal of said circuit and further configured toinitially carry said disable signal having said first value and tosubsequently carry said disable signal having said second value inresponse to a latching of an input for said circuit.
 30. The latchregulator of claim 29, said lockout pathway further configured to carrysaid disable signal having said first value in response to a resettransmission to said circuit.
 31. The latch regulator of claim 29, saidlogic apparatus comprising a NOR gate.
 32. The latch regulator of claim29, said logic apparatus comprising an AND gate.
 33. The latch regulatorof claim 29, said logic apparatus comprising a NAND gate.
 34. A methodfor regulating the ability of a testing circuit to latch output vectors,comprising: latching only in response to changing at least one outputvector; and allowing a change in said output vector only in response tolatching and to resetting said output vector.
 35. A method forregulating the ability of a testing circuit to latch at least one outputvector, comprising: designating one output vector as a lockout vector;allowing at least one latching; associating at least one latching with afirst change of said lockout vector; initiating said first change ofsaid lockout vector; allowing further latching only in response to asecond change of said lockout vector; and allowing said second change inlockout vector only in response to further latching and to resettingsaid lockout vector.
 36. The method in claim 35, wherein: said methodfurther comprises establishing an initial value for said lockout vector;initiating said first change of said lockout vector further compriseschanging said initial value of said lockout vector; and allowing furtherlatching comprises allowing further latching only in response to arestoration of said initial value.
 37. A method of preventing a circuithaving a test mode entry function from entering a subsequent test modeafter said circuit enters a first test mode, comprising: initiating atest mode blocking signal after said circuit completes said first testmode; and exclusively controlling said test mode entry function of saidcircuit with said test mode blocking signal.
 38. The method in claim 37,further comprising generating said test mode blocking signal responsiveto a final test latch of said circuit during said first test mode. 39.The method in claim 38, further comprising originating said test modeblocking signal from said circuit.
 40. A method of preserving a state ofan output of a test vector decode circuit, said test vector decodecircuit configured to change said state of said output in response toreceiving a latch signal, comprising: producing a blocking signal; andisolating said circuit from any latch signal with said blocking signal.41. The method of claim 40, further comprising transmitting saidblocking signal as an output of said circuit.
 42. A method of testing acircuit, comprising: receiving at least one address input; receiving atleast one latching signal; performing a decoding operation on eachaddress input; transmitting a result of said decoding operation as atleast one output test vector in response to each latching signal;driving said circuit with each output test vector; generating a latchprevention signal; and overriding any subsequent latching signal withsaid latch prevention signal.
 43. The method in claim 42, whereingenerating comprises generating said latch prevention signal in responseto transmitting a result of a decoding operation.
 44. The method inclaim 43, further comprising enabling said latch prevention signal to beoverridden.
 45. A method of sustaining a potential of a signal from anoutput pathway of a test vector decode device coupled to a logiccircuit, said logic circuit configured to carry a potential-changingtransmission to said test vector decode device, comprising: maintaininga state of electrical communication between said logic circuit and saidtest vector decode device; and preventing further changes in said stateof electrical communication between said logic circuit and said testvector decode device.
 46. A method for testing an external circuit,comprising: subjecting an address input to a logic function; generatingan output vector; driving said external circuit with said output vector;generating a lockout signal; and prohibiting subjecting an address inputto a logic function during a generation of said lockout signal.
 47. Amethod of regulating the value of a test signal, comprising: initiatinga latch mode; accepting an input signal; performing a logic operation onsaid input signal; deriving an output signal; and initiating an inputlockout mode.
 48. The method in claim 47, further comprising deriving aplurality of output signals, and wherein initiating an input lockoutmode comprises initiating said input lockout mode with one output signalof said plurality of output signals.
 49. The method in claim 48, furthercomprising reestablishing said latch mode through a reset signal. 50.The method in claim 49, further comprising reestablishing said latchmode exclusively through said reset signal.
 51. The method in claim 50,wherein reestablishing said latch mode through said reset signalcomprises resetting said one output signal that initiated said inputlockout mode.
 52. A method of protecting a test circuit from receiving asubsequent latching signal after receiving at least one prior latchingsignal, comprising: allowing at least one prior latching signal to reachsaid test circuit; performing a test circuit operation for each priorlatching signal; providing a lockout signal; and stopping any subsequentlatching signal with said lockout signal.
 53. The method in claim 52,wherein providing said lockout signal further comprises generating saidlockout signal responsive to a last prior latching signal.
 54. A methodof preventing a test vector decode circuit from reentering a test mode,comprising: making a reentry into said test mode dependent upon a changeof an output vector of said test vector decode circuit; and making saidchange of said output vector dependent upon said reentry into said testmode.